Tensilica has announced its eighth-generation tools that further automate customised Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE) and pin-level co-simulation with RTL. 'In the dataplane - as opposed to the control plane - our DPUs have to deal with intensive data processing workloads and direct interconnection to hardware blocks,' said Steve Roddy, Tensilica's vice-president of marketing and business development.'With this eighth-generation tool set, we've concentrated on improvements that make it easier for designers to use customised DPUs to perform these data-intensive tasks, bringing programmability, enhanced debugging and post-silicon software upgradability to signal processing and other dataplane functions previously handled in dedicated hardware blocks,' he added. Tensilica's compiler now supports operator overloading on custom data types in the C programming language, without any of the overhead that is often associated with it.
The compiler also now displays custom data types in their natural format for faster debugging. Tensilica is known for its ability to let designers add custom instructions and data types to its processors to improve performance. If an application needs to work on 56-bit data, a designer can now define a custom 56-bit data type with a single line of code. The designer can also specify what regular C operators, such as '+' and '*', should do when using this data type. The overloading is always done with zero overhead so the resulting binaries are most efficient.
Porting and creating C application code that uses custom data types is now easier as standard C operator syntax can be used. This makes the code easier to read and allows porting via changes in the C header files rather than throughout all of the source code itself. User-defined display formatting (UDDF) provides a means to display non-integer data types (such as fixed point and vectors) in a more natural and readable way that makes debugging issues faster. Custom data types that are pre-defined in Tensilica's audio and communications DSPs, such as Hi-Fi and ConnX D2, already have overloading definitions and pre-defined UDDFs.
Tensilica now allows designers to program, simulate and profile a simple shared memory subsystem for heterogeneous cores quickly within the Xtensa Xplorer IDE. The memory partitioning for each core and the shared memory is simplified by specifying them in the subsystem wizard. With a subsystem defined, it can be simulated and profiled within the IDE for initial assessment of hardware and software partitioning using side-by-side profile comparisons. To aid the designer in dealing with shared memory systems, Tensilica provides a synchronisation library in C source form with primitives for locks, barriers and semaphores.
With this library, up to six months of development and bug fixing can be avoided for designers who are new to shared memory systems. Tensilica has made several improvements to its Xtensa Xplorer IDE so designers now have an upgraded IDE platform (Eclipse 3.3, CDT 4.0) as well as faster simulation speeds and more efficient debugging. The company has also strengthened its simulation capability with the introduction of a link between its pipeline-accurate, cycle-accurate Xtensa Instruction Set Simulator (ISS) and the Verilog simulators. Designers can now run pin-level accurate System-C simulations of Tensilica DPUs in their native Verilog simulators.
