Rutronik Releases Temperature-Sensor IC Range

Rutronik has presented the TSci temperature-sensor IC range from ZMDI, containing fully tested and calibrated sensors with absolute measurement accuracy on delivery. Designed for high-performance, cost-effective solutions, the TSic series is used for sensing temperature in building automation, automotive, industrial, office automation, white goods and low-power/mobile applications.

The TSic series employs a high-precision bandgap reference with PTAT output; a low-power, precision ADC and an on-chip DSP core with EEPROM to precisely calibrate the output temperature signal. They include ICs with two linear analogue signal output options, such as standard 0-1V (supply voltage is 3.0 to 5.5V) or ratiometric (10-90 per cent of supply voltage); or the digital serial output signal for interfacing with microcontrollers.

The TSic 506 has a typical current consumption of 45uA, which leads to typically less than 0.07C temperature-reading error due to self heating of the device.

Austriamicrosystems Unveils In-Vehicle-Network ICs

Austriamicrosystems has launched two in-vehicle-network ICs, the AS8520 and AS8530. The AS8520 is dedicated to LIN slaves, which can be found in car doors, car roof modules, seat modules or similar applications providing the transceiver, diagnosis and backup register access, as well as two relay drivers and a resistive attenuator.

The AS8530 is a general-purpose companion IC for LIN slaves providing the transceiver, a LDO and a shared pin microcontroller interface with window watchdog inside an eight-pin package. The AS8520 provides a LIN 2.1 transceiver with more than 6kV ESD IEC61000-4-2 capability on bus pin, a low drop out linear voltage regulator, for up to 60mA load, from a nominal 6-18V supply voltage with over-voltage capability up to 42V.

It also features two low side relay drivers and a resistive attenuator with disable switch for power saving. A four-wire microcontroller serial interface for device configuration, window watchdog trigger, diagnosis read out and read/write of eight continuously supplied backup registers are additional features of the AS8520.

The AS8530 is a stripped-down version of the AS8520 without the application-specific relay driver and attenuator, providing two-wire shared-pin microcontroller interfaces to provide the same digital features as the AS8520 in an eight-pin package. Both circuits are designed for very low quiescent current of typically 36uA in standby mode.

These LIN companion ICs are claimed to provide good diagnosis capability through the microcontroller interfaces. Continuously powered 64-bit backup memory and highly secure non-latching ESD clamp structure on the bus pin are additional highlights. Both devices are available with 5V or 3.3V regulated output voltage. The AS8520 is available in a 24-pin 6 x 6mm QFN package and the AS8530 is available in an eight-pin epSOIC package. Both ICs are suitable for operating environments from -40C to +125C.

Cadence Improves Virtuoso IC Design Platform

Cadence Design Systems has announced performance, capacity and usability enhancements to its Virtuoso IC design platform. The improvements in Virtuoso IC6.1.4 are said to reduce overall design time while ensuring quality production ICs. This is said to benefit design teams working along the full spectrum of design complexity, from the most advanced-node designs to more traditional chips. The Virtuoso release has been extended to work efficiently at advanced nodes down to 28nm and now supports 64-bit processing for improved capacity and performance.

The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access. It now provides design teams a single common router they can use from start to finish to help ensure consistent results. Additional time-saving, quality-enhancing updates have been made to the Virtuoso Analog Design Environment XL, and Cadence design constraints technology. Integrating the Virtuoso Space-Based Router into the Virtuoso Layout Suite brings the power of a net-capable router to the desk of every layout engineer.

Interactive wire editing and full chip automatic finish routing share the same algorithms, providing a flow for a higher quality of design, from IP module creation though full chip sign-off. Improvements to the Virtuoso Analog Design Environment XL include display capabilities within the product that can now produce more and better datasheets. The Virtuoso Analog Design Environment's ability to analyse multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early on and verify those choices efficiently post implementation.

The Cadence design constraints methodology, which can help engineers reduce layout optimisation and design refinement times by as much as 20 per cent, received a boost in the new release, with enhancements that make it easier to add design constraints. In addition, there are new design constraints specifically geared to address sub-45nm design yield challenges. The release extends the Cadence ExpressPcells capability to support multiple-user sites.

Now customers can use their vast libraries of Skill-parameterised cells anywhere and see up to an eight times performance improvement. Cadence also improved the analogue display technology to handle multi-gigabyte waveform files more efficiently. The company has removed the two-gigabyte limit on waveform databases to account for today's larger, more complex designs. Performance has also been boosted for underlying design rule engines.